(1) Field of the Invention
This invention relates to a method for making a high density DRAM cross point cell and the resulting structure, and particularly to those methods which produce a vertical field effect transistor and capacitor structure.
(2) Description of the Prior Art
As DRAMs are scaled down in dimensions, there is a continuous challenge to maintain a sufficiently high stored charge per capacitor unit area. In order to construct high density DRAMs in a reasonable sized chip area, the cell structures have to change from the conventional planar-type capacitors to either trench capacitors or stack capacitors, in particular beyond the 4 Mbit DRAM era. All efforts to increase capacitance without increasing the planar area of the capacitor can be categorized into building three dimensional capacitor structures to increase the capacitor area without increasing the planar area of the capacitor. There are two major branches of this approach, that is trench capacitors and stacked capacitors. In the category of trench capacitors, when the DRAM is beyond 16 Mbit, the trench needs to be very deep. There are technology and even theoretical physical limitations to processing the deep trenches that would be needed. When the stacked capacitor approach is used to fabricate 16 Mbit DRAMs and beyond, very complicated stacked structures are needed, such as fin structures, crown structures, and so forth.
The one transistor DRAM cell includes a field effect transistor and the capacitor in a three dimensioned structure as envisioned for future cells beyond the 16 Mbit device level. In "Advanced Cell Structures for Dynamic RAMS" by Nicky C. C. Lu, Published in IEEE Circuits and Device Magazine January 1989, pp. 27-36, Dr. Lu gives many types of three dimensional DRAM cell designs which have been known to the art. Particularly, on page 34, FIG. 15 there is shown various three dimensional cells. It is interesting to note that none of these DRAM cells are truly vertical, that is with the capacitor directly above the field effect device or alternatively the field effect device directly above the capacitor. W. F. Richardson et al in "A TRENCH TRANSISTOR CROSS-POINT DRAM CELL" Published in 1985 IEDM 85 pages 714-717 describes a vertical DRAM cell with the field effect device 4 directly above the capacitor 3 which is located within a trench as schematically shown in FIG. 1. There is no known reference to a vertical DRAM memory cell with a capacitor 3 located directly about a MOSFET device 4 as schematically shown in FIG. 2.